Programmable Logic and Asic Achronix Speedster FPGAs for 100G Ethernet

Programmable Logic and Asic Achronix Speedster FPGAs for 100G Ethernet

2013/12/18

Achronix has demonstrated error-free operation of 100G Ethernet functionality using the hard Ethernet IP in its Speedster22i FPGAs.

Speedster22i claim to be the only FPGAs that have hardened IP for communication applications including 100G Ethernet, 100G Interlaken, PCI Express Gen3 x8 and DDR3 memory controllers.

“The hardened IP functions in Speedster22i FPGAs translate directly into power and cost savings for high bandwidth communication applications,” says Achronix’s Steve Mensor, ‘more importantly, the hardened IP functions eliminate the challenges associated with closing timing for these high performance applications.”

Speedster22i FPGAs are built on Intel’s 22nm, 3-D finfet process.

Achronix claims that Speedster22i HD devices consume half the power and are half the cost of competitive high‑end FPGAs for targeted high bandwidth applications.

The 100G Ethernet was demonstrated on the HD1000 device, which has 1 million effective programmable look-up-tables (LUTs).

The HD680 is the second member of the Speedster22i family and will begin shipping in Q1 2014.

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