ST-Ericsson describes three-chip stack

SAN JOSE, Calif. – ST-Ericsson and a French research institute will describe this week a chip stack made up of three die including a Wide I/O DRAM. The effort, using tools and a memory controller from Cadence Design Systems, represents one of the first to stack three devices.

Engineers used through silicon vias to link a Wide I/O DRAM and two identical multi-core SoCs. The stack uses a serial asynchronous communications network with throughput of 550 MTransfers/second on one chip and 200 MT/s between chips.

3-D ICs are widely seen as an important new direction in chip designs to continue silicon scaling without needing to go to new process technologies. To date most work has focused on stacks for two chips or on so-called 2.5-D chips that connected two die placed side-by-side on a substrate.

IBM will describe in February an I/O technique for linking as many as six chips in a paper in February at the International Solid-State Circuits Conference. The IBM through-silicon via uses a low-swing transmitter and gated-diode sense amplifier-based receiver to deliver 5.2 Gbits/s at a power level of 0.50 mW/Gbit/s.

Companies such as IBM, Intel and Samsung that have internal fab, packaging and design expertise are expected to lead the way in 3-D ICs. In that context, the ST-Ericsson design may raise some eyebrows at a 3-D IC event this week.

The stack uses ST-Ericsson's Wioming application processor, an SoC designed for use with the upcoming Wide I/O memory interface being defined by Jedec.  The chip supports 12.8 GBytes/s of memory bandwidth, a 50 percent increase over dual-channel low power DDR2 solutions at 533 MHz while using 20 percent less power, the company said.

ST-Ericsson said future versions of the SoC could support memory throughput up to 34 GBytes/s by increasing the chip's DRAM interface clock frequency to 266MHz and switching to a dual data rate mode

The SoC includes a memory controller block supplied by Cadence. In addition, Cadence provided versions of its Encounter Digital Implementation System, Virtuoso Analog Design Environment, and QRC parasitic extraction tools, customized for 3-D IC designs.

In a recent interview, Chi-Ping Hsu, a Cadence senior vice president, said the company is customizing existing tools for 3-D ICs on an ad hoc basis. It is waiting for chip stacking technology to mature before it delivers standard off-the-shelf tools.

The design team has taped out multiple chips. The paper will be presented by Vincent Guerin, a senior digital design engineer at ST-Ericsson, and Pascal Vivet of the French research group CEA-Leti.
ST-Ericsson describes three-chip stack